CT6053 - Digital Systems Applications (2017/18)
|Module specification||Module approved to run in 2017/18, but may be subject to modification|
|Module title||Digital Systems Applications|
|Module level||Honours (06)|
|Credit rating for module||15|
|School||School of Computing and Digital Media|
|Running in 2017/18||
This module extends the digital design techniques learnt at intermediate level to the use of Application Specific Integrated Circuits. It provides an extensive treatment of the use of Virtual Hardware Description Language using the industry's standard (Xilinx and its associated hardware).
1-To provide students with hands-on experience of semi-custom chip design using both text based and schematic design capture;
2-To develop an understanding of the need for and the stages involved in a structured approach to semi-custom chip design;
3-To provide knowledge of a range of chip design systems and testing tools and their use;
4-To investigate the basic features and applications of a range of industry standard semi-custom chip technologies
5-To introduce the general principles of computer aided digital design;
6-To provide experience of working as part of a development team.
On successful completion of this module students should be able to:
LO1. Create, design, test, document and establish innovative digital system
LO2. Design Complex Synchronous Sequential systems
LO3. Designs and test digital systems (Combinational and Sequential) using VHDL and schematic capture systems;
LO1. Use a Computer Aided Design (CAD) system to enter, simulate and implement a digital system in an industry standard ASIC technology;
LO4. Select an appropriate Application Specific Integrated Circuit (ASIC) technology to perform in a specific digital application;
LO5. Explain the role of Field Programmable Gate Array (FPGA) and similar technologies in the prototyping of digital systems and the influence of manufacturing technology on the design and characterisation of VLSI circuits and systems.
A major case study (50%) and is due in week 12 covering the learning outcomes LO1, 2, 3 ad 5.
A final unseen examination (50%) due in week 15 covering the learning outcomes LO1 to 5.