module specification

This module extends the digital design techniques learnt at intermediate level to the use of Application Specific Integrated Circuits. It provides an extensive treatment of the use of Virtual Hardware Description Language using the industry's standard (Xilinx/Altera and its associated hardware).

CT5051: Advanced Electronic Systems or equivalent

Review of Synchronous and Asynchronous sequential systems (race and hazard), Synchronous sequential design, Variable Entered Map (VEM), Synchronous Counter design, Synchronous Sequential Controller Design. 

Learning Outcomes LO1 , LO2

Register and Register Transfers. Data paths and data flow control. Registers and register manipulations. Register transfer operations including data bus oriented systems. Register transfer notations, HDL representation. Control of register transfers. Modularity and Compositionally, the building blocks of programmable architectures.

Learning Outcomes LO1 , LO2

Algorithmic State Machine (ASM) design method. The role of simulation, functional simulation, timing simulation, verification. Design implementation using traditional (schematic diagram) techniques. HDL representation and synthesis of sequential logic including FSMs. Typical design flows from high level models to circuit implementation, structured design methods and convergent designs. Implementation technologies, including FPLAs.

Learning Outcomes LO3 , LO4

Computer Aided Design Electronic CAD (ECAD) design cycle: specification capture, behavioural simulation, circuit (schematic) synthesis, schematic (gate level) simulation, netlist abstraction, Programmable logic implementations: ROM, PLA & PAL structures and implementation of logic circuits. Selection of target (e.g. specific FPGA /CPLD) and binding to target architecture, layout and routing, design rule compliance, back annotation and simulation, FPGA /CPLD implementation, circuit test and verification, closing the loop between simulation and test.

Learning Outcomes LO3 , LO4

Requirements analysis, partitioning designs into dataflow, system design elaboration and modular design, design refinement, module and system simulation and verification, system implementation, testability and verification.
Complex digital systems, their contents and requirements, Design and implementation methodologies for ASIC technology, Hardware description languages (e.g. VHDL/Verilog), Simulation tools for digital systems.

Learning Outcomes LO3 , LO4

Students will develop understanding and practical investigative skills based on weekly lectures, tutorials and supervised workshops.  The teaching sessions will utilise examples/case studies as a platform for understanding principles related to the module.

The workshops, in particular, are provided to support students in gaining practical experience in effective use electronic equipment and simulation tools, within a dedicated laboratory.

Appropriate blended learning approaches and technologies, such as, the University’s VLE, simulation tools and laboratory equipment will be used to facilitate and support student learning.

Students will be encouraged to keep reflective commentaries on their learning activities and tasks that they carry out to complete their work.

On successful completion of this module students should be able to:

LO1. Explain the role of Field Programmable Gate Array (FPGA) and similar technologies holistically in the prototyping of digital systems and the influence of manufacturing technology on the accurate design and characterisation of VLSI circuits and systems;
LO2. Understand and use relevant technical literature to select an appropriate Application Specific Integrated Circuit (ASIC) technology to perform in a specific digital application;
LO3. Create, design, test, and document innovative digital (combinational and sequential) system using VHDL and schematic capture and evaluate its function;
LO4. Use a Computer Aided Design (CAD) system to enter, simulate and implement a digital system in an industry standard ASIC technology;

This module has two main assessment items; Practical Workshops and Case Study, due in week 13, assesses the learning outcomes LO3 and LO4 of the module. The second and final assessment item is an unseen examination paper due in week 15 of the semester assesses learning outcomes LO1-LO3.  Each assessment item contributes to 50% of module.

Core Text:
Zwolinski M. (2004), “Digital System Design with VHDL”, 2nd Ed. Prentice Hall,  ISBN: 9781405890977  https://www.dawsonera.com/readonline/9781405890977

Other Texts:
Kleitz W., (2014), “Digital Electronics: A Practical Approach with VHDL”, 9th Ed. Pearson New International, ISBN:  9781292025612
https://ebookcentral.proquest.com/lib/londonmet/reader.action?docID=5138182

Kleitz W. et al (2011), “Lab Manual for Digital Electronics: A Practical Approach with VHDL”, Prentice Hall, ISBN 0132160870

Tocci RJ, Widmer NS, Moss GL, (2011), “Digital Systems – Principles and Applications”, Pearson Education Ltd. ISBN: 9780130387936

Ciletti M.D., (2011), “Advanced Digital Design with the Verilog HDL”, Prentice Hall, ISBN: 9780130891617

Kafig, W (2014) “VHDL 101 : Everything You Need to Know to Get Started”, Elsevier Science & Technology, ISBN: 9780080959399
https://ebookcentral.proquest.com/lib/londonmet/reader.action?docID=629996

Thomas FL, (2015) “Digital Fundamentals, Global Edition”, Pearson Education, ISBN: 9781292075990  https://www.dawsonera.com/readonline/9781292075990

Websites: University Library website- https://student.londonmet.ac.uk/library/

Electronic Databases: 
IEEE Xplore / IET Digital Library (IEL) - https://ieeexplore.ieee.org/Xplore/home.jsp
ACDM Digital Library - https://0-dl-acm-org.emu.londonmet.ac.uk/dl.cfm
Wiley Online Library - https://0-www-onlinelibrary-wiley-com.emu.londonmet.ac.uk/